1. Field of the Invention
This invention is related to the field of microprocessors and chip multiprocessors (CMP) and, more particularly, to reconfiguration of cache memory of a processor.
2. Description of the Related Art
Modern microprocessors typically include on-chip cache memory. In many cases, microprocessors include an on-chip hierarchical cache structure that may include level one (L1), level two (L2) and in some cases a level three (L3) cache memory. Typical cache hierarchies may employ a small fast L1, cache that may be used to store the most frequently used cache lines. The L2 may be a larger and possibly slower cache for storing cache lines that are accessed but don't fit in the L1. The L3 cache may be used to store cache lines are accessed but do not fit in the L2 cache. Having a cache hierarchy as described above may improve processor performance by reducing the latencies associated with memory access by the processor core.
However, in certain instances such an improvement in performance may come at a cost. It is well known that modem microprocessors can consume a great deal of power and have high thermal budgets. Cache memories may consume power via static leakage even when they are not used. Thus, the larger the cache the more power consumed.
In an effort to increase efficiency and processor, chip multiprocessors (CMPs) are becoming an emerging technology that is gaining increased popularity. A CMP has two or more processor cores implemented on the same integrated circuit (IC) device. The increase in popularity may be due, at least in part, to the notion that a CMP may be a more efficient use of the millions of transistors that may be included on an integrated circuit than, for example, a more elaborate single processor. For example, by sharing processing loads between processor cores, a CMP may execute some tasks at a lower frequency than that required by some single core processors. Lower frequencies may translate in some cases to savings in power and a reduction in the thermal budget.
Since CMPs include multiple processor cores, they may also include circuitry associated with each core. For example, a CMP may include an L1 and an L2 cache memory for each processor core. Accordingly, for the reasons described above relative to single core microprocessors, the power consumption and thermal budget of a CMP may still be high. Thus, it may be desirable to find ways to reduce power consumption while maintaining processor performance.